1. Technical Field
The present disclosure relates to a high-resolution time-to-digital converter.
2. Discussion of Related Art
A time-to-digital converter (TDC) is used to measure a time difference between a standard signal and a comparison signal. Conventionally, the TDC is used in a laser range finder, and recently the TDC is used in an all-digital phase locked loop (ADPLL).
FIG. 1 is a diagram illustrating a conventional TDC including a signal delay line.
Referring to FIG. 1, the TDC 100 includes a delay line 110 transmitting a first signal, a standard line 120 transmitting a second signal, and comparators 130. The comparators 130 compare voltages of nodes on the delay line 110 with voltages of nodes on the standard line 120. The voltages of nodes on the standard line 120 correspond to the voltages of nodes on the delay line 110, respectively.
A time difference between the first signal and the second signal may be calculated from output signals of the comparators 130.
Each of the delay elements DELAY of the delay line 110 is usually implemented with an inverter, and a delay time of such inverter is about 50 picoseconds. Therefore, the TDC 100 in FIG. 1 may have a resolution of about 50 picoseconds.
The resolution of a TDC is required to be increased in order to implement a high-frequency ADPLL.
FIG. 2 is a diagram illustrating a conventional TDC including a vernier delay line.
The TDC 200 in FIG. 2 differs from the TDC 100 in FIG. 1 in that the TDC 200 in FIG. 2 includes two delay lines 210 and 220. There is a difference between a delay time of a delay element DELAY in the first delay line 210 and a delay time of a delay element DELAY in the second delay line 220. For example, the delay time of the delay element in the first delay line 210 may be about 50 picoseconds and the delay time of the delay element in the second delay line 220 may be about 60 picoseconds.
Therefore, the TDC 200 may have a resolution of about 10 picoseconds.
As described above, a TDC including a vernier delay line may have a higher resolution than a TDC including a single delay line. A relatively large chip size, however, is required to implement the TDC including the vernier delay line. Also, the TDC including the vernier delay line has a narrow range of maximum delay time between two signals, and the TDC including the vernier delay line needs much more power than the TDC having only the single delay line.